View HYB18TC256160BF-25_4798676.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

May 2007
HYB18T C25680 0 BF HYB18T C25616 0 BF
256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products
Internet Data Sheet
Rev. 1.3
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Revision History: Rev. 1.3, 2007-05 All 2 All Adapted internet edition Added product type HYB18TC256800BF Qimonda template update
Previous Revision: Rev. 1.21, 2007-02 Previous Revision: Rev. 1.2, 2006-07
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 07182006-DD60-22E6
2
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics.
1.1
Features
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: * Off-Chip-Driver impedance adjustment (OCD) and On* 1.8 V 0.1 V Power Supply * 1.8 V 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality * DRAM organizations with 8 and 16 data in/outputs * Auto-Precharge operation for read and write bursts * Double Data Rate architecture: two data transfers per * Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes * Programmable CAS Latency: 3, 4, 5 and 6 * Average Refresh Period 7.8 s at a TCASE lower than * Programmable Burst Length: 4 and 8 85 C, 3.9 s between 85 C and 95 C * Differential clock inputs (CK and CK) * Programmable self refresh rate via EMRS2 setting * Programmable partial array refresh via EMRS2 settings * Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read * DCC enabling via EMRS2 setting * Full and reduced Strength Data-Output Drivers data and center-aligned with write data. * 1K page size * DLL aligns DQ and DQS transitions with clock * Packages: PG-TFBGA-84, PG-TFBGA-60 * DQS can be disabled for single-ended data strobe operation * RoHS Compliant Products1) * Commands entered on each positive clock edge, data and * All Speed grades faster than DDR400 comply with data mask are referenced to both edges of DQS DDR400 timing specifications when run at a clock rate of * Data masks (DM) for write data 200 MHz * Posted CAS by programmable additive latency for better command and data bus efficiency
TABLE 1
Performance tables for -2.5
Product Type Speed Code Speed Grade Max. Clock Frequency @CL6 @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -2.5 DDR2-800E 6-6-6 Unit -- MHz MHz MHz MHz ns ns ns ns
fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
400 333 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.3, 2007-05 07182006-DD60-22E6
3
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Performance table for -3(S)
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3 DDR2-667C 4-4-4 -3S DDR2-667D 5-5-5 333 266 200 15 15 45 60 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
333 333 200 12 12 45 57
TABLE 3
Performance table for -3.7
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -3.7 DDR2-533C 4-4-4 Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
TABLE 4
Performance table for -5
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -5 DDR2-400B 3-3-3 Units -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
200 200 200 15 15 40 55
Rev. 1.3, 2007-05 07182006-DD60-22E6
4
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 15 bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style. The DDR2 device operates with a 1.8 V 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in PG-TFBGA package.
The 256-Mb DDR2 DRAM is a high-speed Double-DataRate-Two CMOS DRAM device containing 536,870,912 bits and internally configured as a quad -bank DRAM. The 256Mb device is organized as either 8 Mbit x8 I/O x4 banks or 4 Mbit x16 I/O x4 banks chip. These devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 to Table 4 for performance figures. The device is designed to comply with all DDR2 DRAM key features: 1. Posted CAS with additive latency 2. Write latency = read latency - 1 3. Normal and weak strength data-output driver 4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function
TABLE 5
Ordering Information for Lead-Free Products (RoHS Compliant)
Product Type1) HYB18TC256800BF-2.5 HYB18TC256160BF-2.5 HYB18TC256800BF-3 HYB18TC256160BF-3 HYB18TC256800BF-3S HYB18TC256160BF-3S HYB18TC256800BF-3.7 HYB18TC256160BF-3.7 HYB18TC256800BF-5 HYB18TC256160BF-5 Org. x8 x16 x8 x16 x8 x16 x8 x16 x8 x16 3-3-3 200 DDR2-400B 4-4-4 266 DDR2-533C 5-5-5 333 DDR2-667D 4-4-4 333 DDR2-667C CAS-RCD-RP Latencies2)3)4) 6-6-6 Clock (MHz) 400 Speed DDR2-800E Package PG-TFBGA-60 PG-TFBGA-84 PG-TFBGA-60 PG-TFBGA-84 PG-TFBGA-60 PG-TFBGA-84 PG-TFBGA-60 PG-TFBGA-84 PG-TFBGA-60 PG-TFBGA-84 Note
5)
1) Please check with your Qimonda representative that leadtime and availability of your preferred device type and version meet your project requirements. 2) CAS: Column Address Strobe 3) RCD: Row Column Delay 4) RP: Row Precharge 5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Note: For product nomenclature see Chapter 9 of this data sheet
Rev. 1.3, 2007-05 07182006-DD60-22E6
5
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
2
2.1
Configuration
Chip Configuration for PG-TFBGA-60
This chapter contains the chip configuration, addressing.
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# columns are explained in Table 7 and Table 8 respectively. The ball numbering for the FBGA package is depicted in figures.
TABLE 6
Chip Configuration of DDR2 SDRAM
Ball# Name Ball Type I I I I I I I I I I I I I I I I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12:0, Address Signal 10/Autoprecharge Chip Select Bank Address Bus 1:0 Clock Enable Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Function
Clock Signals x8 organization E8 F8 F2 F7 G7 F3 G8 G2 G3 H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 CK CK CKE RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 Clock Signal CK, CK
Control Signals x8 organizations
Address Signals x8 organizations
Rev. 1.3, 2007-05 07182006-DD60-22E6
6
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Ball# L8
Name A13 NC
Ball Type I - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I PWR PWR PWR PWR AI PWR PWR PWR PWR NC
Buffer Type SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - - - - - - - - - -
Function Address Signal 13 Note: 256 Mbit components and Data Signal 3:0 Note: Bi-directional data bus
Data Signals x8 organization C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 B3 A2 B3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS RDQS RDQS DM
Data Signal 7:4 Note: Bi-directional data bus
Data Strobex8 organizations Data Strobe
Data Strobe x8 organisation Read Data Strobe
Data Mask x8 organizations Data Mask I/O Driver Power Supply Power Supply I/O Driver Power Supply Power Supply I/O Reference Voltage Power Supply Power Supply Power Supply Power Supply Not Connected Note: No internal electrical connection is present On-Die Termination Control Power Supplies x8 organization A9,C1,C3,C7,C VDDQ 9
VDD A7,B2,B8,D2,D VSSQ
A1 8 A3,E3 E2 E1 E9,H9,L1 E7 J1,K9 G1, L3,L7, L8
VSS VREF VDDL VDD VSSDL VSS
NC
Power Supplies x8 organizations
Not Connected x8 organization
Other Balls x8 organizations F9 ODT I SSTL
Rev. 1.3, 2007-05 07182006-DD60-22E6
7
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 7
Abbreviations for Ball Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only ball. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 8
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Rev. 1.3, 2007-05 07182006-DD60-22E6
8
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Chip Configuration for x8 components, PG-TFBGA-60 (top view)
FIGURE 1
Notes 1. 2. 3. 4. RDQS / RDQS are enabled by EMRS(1) command. If RDQS / RDQS is enabled, the DM function is disabled When enabled, RDQS & RDQS are used as strobe signals during reads. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device. 5. Ball position L8 is A13 for 512-Mbit and is Not Connected on 256-Mbit.
Rev. 1.3, 2007-05 07182006-DD60-22E6
9
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
2.2
Chip Configuration for PG-TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# columns are explained in Table 7 and Table 8 respectively.
TABLE 9
Chip Configuration of DDR SDRAM
Ball# Name Ball Type I I I I I I I I I I I I I I I I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12:0,Address Signal 10/Autoprecharge Chip Select Bank Address Bus 1:0 Clock Enable Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Function
Clock Signals x16 Organization J8 K8 K2 K7 L7 K3 L8 L2 L3 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 CK CK CKE RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 Clock Signal CK, CK
Control Signals x16 Organization
Address Signals x16 Organization
Rev. 1.3, 2007-05 07182006-DD60-22E6
10
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I AI PWR
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - -
Function
Data Signals x16 Organization G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 B7 A8 F7 E8 B3 F3 J2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS UDQS LDQS LDQS UDM LDM Data Signal 15:0 Note: Bi-directional data bus. DQ[15:0] for x16 components
Data Strobe x16 Organization Data Strobe Upper Byte Data Strobe Lower Byte
Data Mask x16 Organization Data Mask Upper Byte Data Mask Lower Byte I/O Reference Voltage I/O Driver Power Supply
Power Supplies x16 Organization
VREF C1, C3, C7, C9, VDDQ
E9, G1, G3, G7, G9 J1
VDDL A1, E1, J9, M9, VDD
R1 A7, A9, D2, D8, VSSQ E7, F2, F8, H2, H8 J7
PWR PWR PWR
- - -
Power Supply Power Supply Power Supply
VSSDL
PWR PWR
- -
Power Supply Power Supply
A3, E3, J3, N1, VSS P9 A2, E2, L1, R3, NC R7, R8
Not Connected x16 Organization NC - Not Connected
Rev. 1.3, 2007-05 07182006-DD60-22E6
11
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball Type I
Buffer Type SSTL
Function
Other Balls x16 Organization K9 ODT On-Die Termination Control
TABLE 10
Abbreviations for Ball Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only ball. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 11
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Rev. 1.3, 2007-05 07182006-DD60-22E6
12
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Ball Configuration for x16 components, PG-TFBGA-84 (top view)
FIGURE 2
Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8] 3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ are isolated on the device.
Rev. 1.3, 2007-05 07182006-DD60-22E6
13
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
2.3
256-Mbit DDR2 Addressing
TABLE 12
DDR2 Addressing for x8 Organization
This chapter describes the 256-Mbit DDR2 addressing.
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
1) Referred to as 'org' 2) Referred to as 'colbits' 3) PageSize = 2colbits x org/8 [Bytes]
32Mb x 8 BA[1:0] 4 A10 / AP A[12:0] A[9:0] 10 8
1)
Note
2)
1024 (1K)
3)
TABLE 13
DDR2 Addressing for x16 Organization
Configuration Bank Address Number of Banks Auto-Precharge Row Address Column Address Number of Column Address Bits Number of I/Os Page Size [Bytes]
1) Referred to as 'org' 2) Referred to as 'colbits' 3) PageSize = 2colbits x org/8 [Bytes]
16Mb x 16 BA[1:0] 4 A10 / AP A[12:0] A[8:0] 9 16 1024 (1K)
1)
Note
2)
3)
Rev. 1.3, 2007-05 07182006-DD60-22E6
14
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
This chapter contains the functional description.
TABLE 14
Mode Register Definition (BA[2:0] = 000B)
Field BA2 Bits 16 Type1) reg. addr. Description Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA1 BA0 A13 15 14 13 BA2 Bank Address Bank Address [1] BA1 Bank Address 0B Bank Address [0] 0B BA0 Bank Address Address Bus[13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B PD 12 w A13 Address bit 13 Active Power-Down Mode Select 0B PD Fast exit 1B PD Slow exit Write Recovery2) Note: All other bit combinations are illegal. 001B 010B 011B 100B 101B DLL 8 w WR 2 WR 3 WR 4 WR 5 WR 6
WR
[11:9]
w
DLL Reset 0B DLL No 1B DLL Yes Test Mode 0B TM Normal Mode 1B TM Vendor specific test mode
TM
7
w
Rev. 1.3, 2007-05 07182006-DD60-22E6
15
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Field CL
Bits [6:4]
Type1) w
Description CAS Latency Note: All other bit combinations are illegal. 011B 100B 101B 110B 111B CL 3 CL 4 CL 5 CL 6 CL 7
BT
3
w
Burst Type 0B BT Sequential BT Interleaved 1B Burst Length Note: All other bit combinations are illegal. 010B BL 4 011B BL 8
BL
[2:0]
w
1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.
TABLE 15
Extended Mode Register Definition (BA[2:0] = 001B)
Field BA2 Bits 16 Type1) reg. addr. Description Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA1 BA0 A13 15 14 13 w BA2 Bank Address Bank Address [1] 0B BA1 Bank Address Bank Address [0] 1B BA0 Bank Address Address Bus [13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B Qoff 12 w A13 Address bit 13 Output Disable 0B QOff Output buffers enabled 1B QOff Output buffers disabled Read Data Strobe Output (RDQS, RDQS) RDQS Disable 0B 1B RDQS Enable
RDQS
11
w
Rev. 1.3, 2007-05 07182006-DD60-22E6
16
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Field DQS
Bits 10
Type1) w
Description Complement Data Strobe (DQS Output) 0B DQS Enable DQS Disable 1B Off-Chip Driver Calibration Program 000B OCD OCD calibration mode exit, maintain setting 001B OCD Drive (1) 010B OCD Drive (0) 100B OCD Adjust mode 111B OCD OCD calibration default Additive Latency Note: All other bit combinations are illegal. 000B 001B 010B 011B 100B 101B AL 0 AL 1 AL 2 AL 3 AL 4 AL 5
OCD [9:7] Program
w
AL
[5:3]
w
RTT
6,2
w
Nominal Termination Resistance of ODT Note: See Table 26 "ODT DC Electrical Characteristics" on Page 24 00B 01B 10B 11B RTT (ODT disabled) RTT 75 Ohm RTT 150 Ohm RTT 50 Ohm
DIC
1
w
Off-chip Driver Impedance Control DIC Full (Driver Size = 100%) 0B 1B DIC Reduced DLL Enable 0B DLL Enable 1B DLL Disable
DLL
0
w
1) w = write only register bits
Rev. 1.3, 2007-05 07182006-DD60-22E6
17
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 16
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field BA Bits [15:14] Type1) w Description Bank Adress 00B BA MRS 01B BA EMRS(1) 10B BA EMRS(2) 11B BA EMRS(3): Reserved Address Bus, High Temperature Self Refresh Rate for TCASE > 85C 0B A7 disable 1B A7 enable 2) Address Bus 000B A Address bits Address Bus, Duty Cycle Correction (DCC) 0B A3 DCC disabled 1B A3 DCC enabled Address Bus, Partial Array Self Refresh for 4 Banks3) Note: Only for 256 Mbit and 512 Mbit components 000B 001B 010B 011B 100B 101B 110B 111B PASR0 Full Array PASR1 Half Array (BA[1:0]=00, 01) PASR2 Quarter Array (BA[1:0]=00) PASR3 Not defined PASR4 3/4 array (BA[1:0]=01, 10, 11) PASR5 Half array (BA[1:0]=10, 11) PASR6 Quarter array (BA[1:0]=11) PASR7 Not defined
SRF
7
w
A DCC
[6:4] 3
w w
Partial Self Refresh for 4 banks PASR [2:0] w
1) w = write only 2) When DRAM is operated at 85 C TCase 95 C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh mode can be entered. 3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
Rev. 1.3, 2007-05 07182006-DD60-22E6
18
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 17
EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B)
Field BA2 Bits 16 Type1) reg.addr Description Bank Address[2] Note: BA2 is not available on 256Mbit and 512Mbit components 0B BA1 BA0 A 15 14 [13:0] w BA2 Bank Address Bank Adress[1] 1B BA1 Bank Address Bank Adress[0] BA0 Bank Address 1B Address Bus[13:0] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 00000000000000BA[13:0] Address bits
1) w = write only
TABLE 18
ODT Truth Table
Input Pin x8 Components DQ[7:0] DQS DQS RDQS RDQS DM x16 Components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM X X X 0 X 0 X X X X X X 0 X 0 X X 1 1 0 EMRS(1) Address Bit A10 EMRS(1) Address Bit A11
Note: X = don't care; 0 = bit set to low; 1 = bit set to high
Rev. 1.3, 2007-05 07182006-DD60-22E6
19
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 19
Burst Length and Sequence
Burst Length 4 Starting Address (A2 A1 A0) x00 x01 x1 0 x1 1 8 000 001 010 011 100 101 110 111 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Rev. 1.3, 2007-05 07182006-DD60-22E6
20
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two SDRAM.
TABLE 20
Command Truth Table
Function CKE Previous Cycle (Extended) Mode Register Set Auto-Refresh Self-Refresh Entry Self-Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge No Operation Device Deselect Power Down Entry Power Down Exit H H H L H H H H H H H H H H L Current Cycle H H L H H H H H H H H X X L H L L L H L L L L L L L L L H H L H L L L L X H L L L H H H H H X X H X H CS RAS CAS WE BA0 BA1 A[12:11] A10 A[9:0] Note1)2)3)
L L L X H H H H L L L L H X X H X H
L H H X H L L H L L H H H X X H X H
BA X X X BA X BA BA BA BA BA X X X X
OP Code X X X X X Column Column Column Column X X X X X X X L H L H L H X X X X X X X X X Column Column Column Column X X X X
4)5)
4) 4)6) 4)6)7)
4)5) 4) 4)5) 4)5)8) 4)5)8)
Row Address
4)5)8) 4)5)8)
4) 4) 4)9)
4)9)
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 2) "X" means "H or L (but a defined logic level)". 3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode Register. 6) VREF must be maintained during Self Refresh operation. 7) Self Refresh Exit is asynchronous. 8) Burst reads or writes at BL = 4 cannot be terminated. 9) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements.
Rev. 1.3, 2007-05 07182006-DD60-22E6
21
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 21
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE Previous Cycle6) (N-1) Power-Down Self Refresh Bank(s) Active All Banks Idle L L L L H H H Any State other than listed above
1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11)
Current Cycle6) (N) L H L H L L L H
Command (N)2) 3) RAS, CAS, WE
Action (N)2)
Note4)5)
X DESELECT or NOP X DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTOREFRESH
Maintain Power-Down Power-Down Exit Maintain Self Refresh Self Refresh Exit Active Power-Down Entry Precharge Power-Down Entry Self Refresh Entry
7)8)11) 7)9)10)11) 8)11)12) 9)11)12)13)14) 7)9)10)11)15) 9)10)11)15)
7)11)14)16) 17)
H
Refer to the Command Truth Table
12) 13) 14) 15) 16) 17)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. CKE must be maintained HIGH while the device is in OCD calibration mode. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to "1" in EMRS(1)). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. VREF must be maintained during Self Refresh operation. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table.
TABLE 22
Data Mask (DM) Truth Table
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM L H
DQs Valid X
Note
1) 1)
Rev. 1.3, 2007-05 07182006-DD60-22E6
22
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
5
5.1
Electrical Characteristics
Absolute Maximum Ratings
TABLE 23
Absolute Maximum Ratings
This chapter describes the electrical characteristics.
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 23 at any time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
VDD VDDQ VDDL VIN, VOUT TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS
-1.0 -0.5 -0.5 -0.5
V V V V C
1) 1)2) 1)2) 1) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 24
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 95 C
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.3, 2007-05 07182006-DD60-22E6
23
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
TABLE 25
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating Min. Typ. 1.8 1.8 1.8 0.5 x VDDQ Max. 1.9 1.9 1.9 0.51 x VDDQ
Unit
Note
VDD VDDDL VDDQ VREF VTT
1) 2) 3) 4)
Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage
1.7 1.7 1.7 0.49 x VDDQ
V V V V
1) 1) 1) 2)3)
4) Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. Peak to peak ac noise on VREF may not exceed 2% VREF (dc) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF.
TABLE 26
ODT DC Electrical Characteristics
Parameter / Condition Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Deviation of VM with respect to VDDQ / 2
1)
Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM
Min. 60 120 40 -6.00
Nom. 75 150 50 --
Max. 90 180 60 + 6.00
Unit %
Note
1)
1)
1)
2)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) - VIL(ac)) /(I(VIHac) - I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) - 1) x 100%
TABLE 27
Input and Output Leakage Currents
Symbol Parameter / Condition Input Leakage Current; any input 0 V < VIN < VDD Output Leakage Current; 0 V < VOUT < VDDQ Min. -2 -5 Max. +2 +5 Unit A A Note
1) 2)
IIL IOL
1) All other pins not under test = 0 V 2) DQ's, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Rev. 1.3, 2007-05 07182006-DD60-22E6
24
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don't care.
DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
TABLE 28
DC & AC Logic Input Levels for DDR2-667 and DDR2-800
Symbol Parameter DDR2-667, DDR2-800 Min. Max. Units
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
DC input logic high DC input low AC input logic high AC input low
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
V V V V
VREF + 0.200
--
VREF - 0.200
TABLE 29
DC & AC Logic Input Levels for DDR2-533 and DDR2-400
Symbol Parameter DDR2-533, DDR2-400 Min. Max. Units
VIH(dc) VIL(dc) VIH(ac) VIL(ac)
DC input logic high DC input low AC input logic high AC input low
VREF + 0.125
-0.3
VDDQ + 0.3 VREF - 0.125
--
V V V V
VREF + 0.250
--
VREF - 0.250
TABLE 30
Single-ended AC Input Test Conditions
Symbol Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum Slew Rate Value 0.5 x VDDQ 1.0 1.0 Unit V V V / ns Note
1) 1) 2)3)
VREF VSWING.MAX
SLEW
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to VIL(ac).MAX for falling edges as shown in Figure 3 3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions.
Rev. 1.3, 2007-05 07182006-DD60-22E6
25
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 3
Single-ended AC Input Test Conditions Diagram
TABLE 31
Differential DC and AC Input and Output Logic Levels
Symbol Parameter DC input signal voltage DC differential input voltage AC differential input voltage AC differential cross point input voltage AC differential cross point output voltage Min. -0.3 0.25 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 Max. Unit -- -- V V V Note
1) 2) 3) 4) 5)
VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac)
1) 2) 3) 4)
VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125
indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR- VCP required for switching. The minimum value is equal to VIH(dc) - VIL(dc). VID(ac) specifies the input differential voltage VTR - VCP required for switching. The minimum value is equal to VIH(ac) - VIL(ac). The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
Rev. 1.3, 2007-05 07182006-DD60-22E6
26
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 4
Differential DC and AC Input and Output Logic Levels Diagram
5.4
Output Buffer Characteristics
TABLE 32
SSTL_18 Output DC Current Drive
This chapter describes the Output Buffer Characteristics.
Symbol
Parameter Output Minimum Source DC Current
SSTL_18 -13.4
Unit mA
Note
1)2)
2)3) Output Minimum Sink DC Current 13.4 mA 1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT-VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
IOH IOL
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement. 3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
TABLE 33
SSTL_18 Output AC Test Conditions
Symbol Parameter Minimum Required Output Pull-up Maximum Required Output Pull-down SSTL_18 Unit V V Note
1) 1)
Output Timing Measurement Reference Level V 1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that 335 mV must be developed across the effectively
25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA x 45 Ohm = 603 mV).
VOH VOL VOTR
VTT + 0.603 VTT - 0.603 0.5 x VDDQ
Rev. 1.3, 2007-05 07182006-DD60-22E6
27
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 34
OCD Default Characteristics
Symbol -- -- -- Description Output Impedance Pull-up / Pull down mismatch Output Impedance step size for OCD calibration Min. 0 0 1.5 Nominal -- -- -- Max. 4 1.5 5.0 Unit V / ns Note
1)2) 1)2)3) 4)
See Chapter 5.5
Output Slew Rate 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
SOUT
1)5)6)7)
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT-VDDQ) / IOH must be less than 23.4 Ohm for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = -280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV. 3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage. 4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 0.75 Ohms under nominal conditions. 5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC. This is verified by design and characterization but not subject to production test. 6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ's is included in tDQSQ and tQHS specification. 7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Rev. 1.3, 2007-05 07182006-DD60-22E6
28
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
TABLE 35
Input / Output Capacitance for DDR2-800
This chapter contains the input / output capacitance.
Symbol
Parameter
DDR2-800 Min. Max. Unit pF pF pF pF pF pF
CCK CDCK CI CDI CIO CDIO
Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS
1.0
--
1.0
--
2.0 0.25 1.75 0.25 3.5 0.5
2.5
--
TABLE 36
Input / Output Capacitance for DDR2-667
Symbol Parameter DDR2-667 Min. CCK CDCK CI CDI CIO CDIO Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS Max. Unit pF pF pF pF pF pF
1.0
--
1.0
--
2.0 0.25 2.0 0.25 3.5 0.5
2.5
--
Rev. 1.3, 2007-05 07182006-DD60-22E6
29
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 37
Input / Output Capacitance for DDR2-533
Symbol Parameter DDR2-533 Min. CCK CDCK CI CDI CIO CDIO Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS Max. Unit pF pF pF pF pF pF
1.0
--
1.0
--
2.0 0.25 2.0 0.25 4.0 0.5
2.5
--
TABLE 38
Input / Output Capacitance for DDR2-400
Symbol Parameter DDR2-400 Min. CCK CDCK CI CDI CIO CDIO Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS Max. Unit pF pF pF pF pF pF
1.0
--
1.0
--
2.0 0.25 2.0 0.25 4.0 0.5
2.5
--
Rev. 1.3, 2007-05 07182006-DD60-22E6
30
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
6
Specifications and Conditions
TABLE 39
IDD Specification Parameters and Test Conditions
This chapter describes the Current Measurement, Specifications and Conditions.
Parameter Operating Current - One bank Active - Precharge tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching.
Symbol
Note
1)2)3)4)5)6)
IDD0
IDD1
1)2)3)4)5)6)
Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are floating. Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching, Data bus inputs are switching. Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data bus inputs are floating. Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating. MRS A12 bit is set to "0" (Fast Power-down Exit). Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
IDD3P(0)
1)2)3)4)5)6)
IDD3P(1)
1)2)3)4)5)6)
Active Standby Current IDD3N All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA. Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; Burst Refresh Current IDD5B tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. Distributed Refresh Current IDD5D tCK = tCK(IDD), Refresh command every tREFI = 7.8 s interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching.
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
Rev. 1.3, 2007-05 07182006-DD60-22E6
31
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
Note
1)2)3)4)5)6)
IDD6 Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating.
Operating Bank Interleave Read Current IDD7 All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 x tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data pattern is same as IDD4R; Refer to the following pages for detailed timing conditions 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled.
4) 5) 6) 7) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. For IDD definition see Table 40 Timing parameter minimum and maximum values for IDD current measurements are defined in Chapter 7. A - Activate, RA - Read with Auto-Precharge, D - Deselect
1)2)3)4)5)6)7)
TABLE 40
Definition for IDD
Parameter LOW HIGH STABLE FLOATING SWITCHING Description Defined as VIN VIL(AC).MAX Defined as VIN VIH(AC).MIN Defined as inputs are stable at a HIGH or LOW level Defined as inputs are VREF = VDDQ / 2 Defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes
Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. Legend: A - Active; RA - Read with Autoprecharge; D - Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and ttFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during Deselect. IOUT = 0 mA Timing Patterns for 4 bank devices with 1 KB or 2 KB page size -DDR2-400 4-4-4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D -DDR2-400 3-3-3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D -DDR2-533 4-4-4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D -DDR2-533 3-3-3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D -DDR2-667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D -DDR2-667 4-4-4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D -DDR2-800 6-6-6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D -DDR2-800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
Rev. 1.3, 2007-05 07182006-DD60-22E6
32
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
-DDR2-800 4-4-4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D -DDR2-1066 7-7-7: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D -DDR2-1066 6-6-6: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D
TABLE 41
IDDSpecification
Symbol -2.5 DDR2-800E -3 DDR2-667C 95 105 7 45 40 33 9 50 155 170 140 9 7 252 -3S DDR2-667D 90 100 7 45 40 33 9 50 155 170 140 9 7 240 -3.7 DDR2-533C 80 90 7 38 35 28 9 43 130 145 130 9 7 230 -5 DDR2-400B 75 83 7 34 32 24 9 39 115 130 125 9 7 220 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
3) 3) 1) 2)
Unit
Note
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
100 115 7 51 45 39 9 60 180 200 145 9 7 255
1) MRS(12)=0 2) MRS(12)=1 3) 0 TCASE 85C.
Rev. 1.3, 2007-05 07182006-DD60-22E6
33
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
7
7.1
Timing Characteristics
Speed Grade Definitions
TABLE 42
Speed Grade Definition Speed Bins for DDR2-800E
This chapter contains speed grade definition, AC timing parameter and ODT tables.
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications (tCK = 5ns with tRAS = 40ns).
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol
DDR2-800E -2.5 6-6-6 Min. 5 3.75 3 2.5 45 60 15 15 Max. 8 8 8 8 70000 -- -- --
Unit
Note
tCK
-- ns ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the "Reference Load for Timing Measurements". 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.3, 2007-05 07182006-DD60-22E6
34
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 43
Speed Grade Definition Speed Bins for DDR2-667
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-667C -3 4-4-4 Min. 5 3 3 45 57 12 12 Max. 8 8 8 70000 -- -- -- DDR2-667D -3S 5-5-5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) imings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the "Reference Load for Timing Measurements". 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 44
Speed Grade Definition Speed Bins for DDR2-533C
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the "Reference Load for Timing Measurements". 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined.
Rev. 1.3, 2007-05 07182006-DD60-22E6
35
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 45
Speed Grade Definition Speed Bins for DDR2-400B
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8.Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the "Reference Load for Timing Measurements" according to Chapter 8.1 only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined in Chapter 8.3. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. See section 8 for the reference load for timing measurements. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.3, 2007-05 07182006-DD60-22E6
36
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
7.2
Component AC Timing Parameters
TABLE 46
DRAM Component Timing Parameter by Speed Grade - DDR2-800
List of Timing Parameters Tables.
Parameter
Symbol
DDR2-800 Min. Max. +400 -- 0.52 8000 -- 0.52 -- -- -- -- +350 -- -- 200 + 0.25 -- -- -- __
Unit
Note1)2)3)4)5)6)7)
DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width
tAC tCCD tCH.AVG tCK.AVG tCKE
-400 2 0.48 2500 3 0.48 WR + tnRP
ps
8)
nCK tCK.AVG
ps
9)10) 9)10) 11)
nCK tCK.AVG nCK
ns ps
tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW DQ and DM input hold time
9)10) 12)13)
tIS + tCK .AVG + tIH
125 0.35 -350 0.35 0.35 -- - 0.25 50 0.2 0.2 Min(tCH.ABS, tCL.ABS) -- 250 0.6 175 2 x tAC.MIN
tDH.BASE DQ and DM input pulse width for each input tDIPW DQS output access time from CK / CK tDQSCK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS
edges DQ and DM input setup time DQS falling edge hold time from CK DQS falling edge to CK setup time CK half pulse width Data-out high-impedance time from CK / CK
18)19)14)
tCK.AVG
ps
8)
tCK.AVG tCK.AVG
ps
15) 16)
tCK.AVG
ps
tDS.BASE tDSH tDSS tHP
17)18)19) 16) 16) 20)
tCK.AVG tCK.AVG
ps ps ps
tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD OCD drive mode output delay tOIT DQ/DQS output hold time from DQS tQH DQ hold skew factor tQHS
tAC.MAX
-- -- -- tAC.MAX
8)21) 22)24)
tCK.AVG
ps ps ps ns
23)24) 8)21) 8)21) 34)
tAC.MIN
0 2 0
tAC.MAX
12 -- 12 -- 300
nCK
ns ps ps
34) 25) 26)
tHP - tQHS
--
Rev. 1.3, 2007-05 07182006-DD60-22E6
37
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2-800 Min. Max. 7.8 3.9 -- -- 1.1 0.6 -- -- 0.6 -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)6)7)
Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges
tREFI tRFC tRP tRPRE tRPST tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WL
-- -- 75
s s ns ns
27)28) 28)29) 30)
tRP
0.9 0.4 7.5 0.35 0.4 15 7.5 2 8 - AL 2
tCK.AVG tCK.AVG
ns
31)32) 31)33) 34)
tCK.AVG tCK.AVG
ns ns
34) 34)35)
nCK nCK nCK
ns
34)
tRFC +10
200 RL - 1
nCK nCK
1) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations of Chapter 7.3). 11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.
Rev. 1.3, 2007-05 07182006-DD60-22E6
38
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 6. 15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 6. 18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 7. 23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 7. 24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 25) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 27) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 28) 0 C TCASE 85 C 29) 85 C < TCASE 95 C 30) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 5 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
Rev. 1.3, 2007-05 07182006-DD60-22E6
39
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
TABLE 47
DRAM Component Timing Parameter by Speed Grade - DDR2-667
Parameter Symbol DDR2-667 Min. DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width Max. +450 -- 0.52 8000 -- 0.52 -- -- -- -- +400 -- -- 240 + 0.25 -- -- -- __ ps
8)
Unit
Note1)2)3)4)5)6)7)
tAC tCCD tCH.AVG tCK.AVG tCKE
-450 2 0.48 3000 3 0.48 WR + tnRP
nCK tCK.AVG
ps
9)10)
nCK tCK.AVG nCK
ns ps
11)
tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW DQ and DM input hold time
9)10) 12)13)
tIS + tCK .AVG + tIH
175 0.35 -400 0.35 0.35 -- - 0.25 100 0.2 0.2 Min(tCH.ABS, tCL.ABS) -- 275 0.6 200 2 x tAC.MIN
tDH.BASE DQ and DM input pulse width for each input tDIPW DQS output access time from CK / CK tDQSCK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS
edges DQ and DM input setup time DQS falling edge hold time from CK DQS falling edge to CK setup time CK half pulse width Data-out high-impedance time from CK / CK
18)19)14)
tCK.AVG
ps
8)
tCK.AVG tCK.AVG
ps
15) 16)
tCK.AVG
ps
tDS.BASE tDSH tDSS tHP
17)18)19) 16) 16) 20)
tCK.AVG tCK.AVG
ps ps ps
tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD OCD drive mode output delay tOIT DQ/DQS output hold time from DQS tQH
tAC.MAX
-- -- --
8)21) 24)22)
tCK.AVG
ps ps ps ns
23)24) 8)21) 8)21) 34)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 --
nCK
ns ps
34) 25)
tHP - tQHS
Rev. 1.3, 2007-05 07182006-DD60-22E6
40
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2-667 Min. Max. 340 7.8 3.9 -- -- 1.1 0.6 -- -- 0.6 -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)6)7)
DQ hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges 1) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V.
tQHS tREFI tRFC tRP tRPRE tRPST tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WL
-- -- -- 75
ps s s ns ns
26) 27)28) 28)29) 30)
tRP
0.9 0.4 7.5 0.35 0.4 15 7.5 2 7 - AL 2
tCK.AVG tCK.AVG
ns
31)32) 31)33) 34)
tCK.AVG tCK.AVG
ns ns
34) 34)35)
nCK nCK nCK
ns
34)
tRFC +10
200 RL-1
nCK nCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations of Chapter 7.3).
Rev. 1.3, 2007-05 07182006-DD60-22E6
41
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 6. 15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 6. 18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 7. 23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 7. 24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 25) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 27) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 28) 0 C TCASE 85 C 29) 85 C < TCASE 95 C 30) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 5 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
Rev. 1.3, 2007-05 07182006-DD60-22E6
42
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
Rev. 1.3, 2007-05 07182006-DD60-22E6
43
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 5
Method for calculating transitions and endpoint
FIGURE 6
Differential input waveform timing - tDS and tDS
FIGURE 7
Differential input waveform timing - tlS and tlH
Rev. 1.3, 2007-05 07182006-DD60-22E6
44
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 48
DRAM Component Timing Parameter by Speed Grade - DDR2-533
Parameter Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- ps Unit Note1)2)3)4)5)
6)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-500 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
7)17)
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
8)
9)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
10)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base)
tCK
ps
tCK
ps
10)
tCK
ps ps
10)
DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK MRS command to ODT update delay Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor
10)
tDSH
tCK tCK
--
11) 12) 10)
DQS falling edge to CK setup time (write cycle) tDSS
tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMOD tMRD tOIT tQH tQHS
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps ns
10) 13) 13)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 400
tCK
ns -- ps
tHP -tQHS
--
Rev. 1.3, 2007-05 07182006-DD60-22E6
45
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2-533 Min. Max. 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)
6)
Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with AutoPrecharge 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V.
tREFI tREFI tRFC tRP tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WR
-- -- 75
s s ns ns
13)14) 15)17) 16)
tRP
0.9 0.40 7.5 10 7.5 0.25 0.40 15 7.5 2 6 - AL 2
tCK tCK
ns ns ns
13) 13) 13)17)
15)21)
tCK tCK
ns ns
18)
19) 20)
tCK tCK tCK
ns
20)
tRFC +10
200
tWR/tCK
tCK tCK
21)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
Rev. 1.3, 2007-05 07182006-DD60-22E6
46
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 14) 0 C TCASE 85 C 15) 85 C < TCASE 95 C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 "Ordering Information for Lead-Free Products (RoHS Compliant)" on Page 5. 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS.
TABLE 49
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Parameter Symbol DDR2-400 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +600 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 350 + 0.25 -- -- ps Unit Note1)2)3)4)5)
6)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-600 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
7)20)
tIS + tCK + tIH
275 -25 0.35 -500 0.35 -- - 0.25 150 -25
8)
9)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data strobe)
10)
tDIPW tDQSCK tDQSL,H tDQSQ
tCK
ps
tCK
ps
10)
Write command to 1st DQS latching transition tDQSS
tCK
ps ps
10)
tDS(base) tDS1(base)
10)
Rev. 1.3, 2007-05 07182006-DD60-22E6
47
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2-400 Min. Max. -- --
Unit
Note1)2)3)4)5)
6)
DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK MRS command to ODT update delay Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command
tDSH
0.2 0.2 MIN. (tCL, tCH) -- 475 0.6 350 2 x tAC.MIN
tCK tCK
--
11) 12) 10)
DQS falling edge to CK setup time (write cycle) tDSS
tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMOD tMRD tOIT tQH tQHS tREFI tREFI tRFC tRP tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps ns
10) 13) 13)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 450 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- --
tCK
ns -- ps s s ns ns
13)14) 15)17) 16)
tHP -tQHS
-- -- -- 75
tRP
0.9 0.40 7.5 10 7.5 0.25 0.40 15 10 2 6 - AL 2
tCK tCK
ns ns ns
13) 13) 13)17)
15)21)
tCK tCK
ns ns
18)
19) 20)
tCK tCK tCK
ns
20)
tRFC +10
Rev. 1.3, 2007-05 07182006-DD60-22E6
48
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2-400 Min. Max. -- --
Unit
Note1)2)3)4)5)
6)
Exit Self-Refresh to Read command Write recovery time for write with AutoPrecharge 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V.
tXSRD
WR
200
tWR/tCK
tCK tCK
21)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 14) 0 C TCASE 85 C 15) 85 C < TCASE 95 C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 "Ordering Information for Lead-Free Products (RoHS Compliant)" on Page 5. 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Rev. 1.3, 2007-05 07182006-DD60-22E6
49
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
7.3
Jitter Definition and Clock Jitter Specification
Generally, jitter is defined as "the short-term variation of a signal with respect to its ideal position in time". The following table provides an overview of the terminology.
TABLE 50
Average Clock and Jitter Symbols and Definition
Symbol Parameter Description Units ps
tCK.AVG
Average clock period tCK.AVG is calculated as the average clock period within any consecutive 200-cycle window:
N 1 . tCK.AVG = --- tCK j N j = 1
N = 200
(1)
tJIT.PER
Clock-period jitter
tJIT.PER is defined as the largest deviation of any single tCK from tCK.AVG: tJIT.PER = Min/Max of {tCKi - tCK.AVG} where i = 1 to 200
ps
tJIT(PER, LCK)
Clock-period jitter during DLL-locking period Cycle-to-cycle clock period jitter
tJIT.PER defines the single-period jitter when the DLL is already locked. tJIT.PER is not guaranteed through final production testing. tJIT(PER,LCK) uses the same definition as tJIT.PER, during the DLL-locking ps
period only.
tJIT.CC
tJIT(PER,LCK) is not guaranteed through final production testing. tJIT.CC is defined as the absolute difference in clock period between two
consecutive clock cycles: tJIT.CC = Max of ABS{tCKi+1 - tCKi}
ps
tJIT(CC, LCK)
Cycle-to-cycle clock period jitter during DLL-locking period Cumulative error across 2 cycles
tJIT.CC defines the cycle- to- cycle jitter when the DLL is already locked. tJIT.CC is not guaranteed through final production testing. tJIT(CC,LCK) uses the same definition as tJIT.CC during the DLL-locking
period only. tJIT(CC,LCK) is not guaranteed through final production testing.
ps
tERR.2PER
tERR.2PER is defined as the cumulative error across 2 consecutive cycles from tCK.AVG:
ps
i + n - 1 tERR ( 2per ) = tCK j - n x tCK ( avg ) j=i
n = 2 for tERR(2per) where i = 1 to 200
(2)
Rev. 1.3, 2007-05 07182006-DD60-22E6
50
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Symbol
Parameter Cumulative error across n cycles
Description
Units ps
tERR.nPER
tERR.2PER is defined as the cumulative error across n consecutive cycles from tCK.AVG:
i + n - 1 tERR ( nper ) = tCK j - n x tCK ( avg ) j=i
where, i = 1 to 200 and n = 3 for tERR.3PER n = 4 for tERR.4PER n = 5 for tERR.5PER 6 n 10 for tERR.6-10PER 11 n 50 for tERR.11-50PER
(3)
tCH.AVG
Average high-pulse width
tCH.AVG is defined as the average high-pulse width, as calculated across
any consecutive 200 high pulses:
tCK.AVG
N 1 . tCH ( avg ) = ---------------------------------------- tCH j ( N x tCK ( avg ) ) j = 1
N = 200
(4)
tCL.AVG
Average low-pulse width
tCL.AVG is defined as the average low-pulse width, as calculated across any tCK.AVG
consecutive 200 low pulses:
N 1 tCL ( avg ) = --------------------------------------- . tCL j ( N x tCK ( avg ) ) j = 1
N = 200
(5)
tJIT.DUTY
Duty-cycle jitter
tJIT.DUTY = Min/Max of {tJIT.CH , tJIT.CL}, where: tJIT.CH is the largest deviation of any single tCH from tCH.AVG tJIT.CL is the largest deviation of any single tCL from tCL.AVG tJIT.CH = {tCHi - tCH.AVG x tCK.AVG} where i=1 to 200 tJIT.CL = {tCLi - tCL.AVG x tCK.AVG} where i=1 to 200
ps
The following parameters are specified per their average values however, it is understood that the following relationship between the average timing and the absolute instantaneous timing holds all the time.
TABLE 51
Absolute Jitter Value Definitions
Symbol Parameter Clock period Clock high-pulse width Clock low-pulse width Min. Max. Unit ps ps ps
tCK.ABS tCH.ABS tCL.ABS
tCK.AVG(Min) + tJIT.PER(Min) tCK.AVG(Max) + tJIT.PER(Max) tCH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCH.AVG(Max) x tCK.AVG(Max) + tJIT.DUTY(Max) tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max) + tJIT.DUTY(Max)
Rev. 1.3, 2007-05 07182006-DD60-22E6
51
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Example: for DDR2-667, tCH.ABS(Min) = (0.48 x 3000ps) - 125 ps = 1315 ps = 0.438 x 3000 ps. Table 64 shows clock-jitter specifications.
TABLE 52
Clock-Jitter Specifications for -667 and -800
Symbol Parameter DDR2 -667 Min. Max. 8000 +125 +100 +250 +200 +175 +225 +250 +250 +350 +450 0.52 0.52 +125 DDR2 -800 Min. 2500 -100 -80 -200 -160 -150 -175 -200 -200 -300 -450 0.48 0.48 -100 Max. 8000 +100 +80 +200 +160 +150 +175 +200 +200 +300 +450 0.52 0.52 +100 ps ps ps ps ps ps ps ps ps ps ps Unit
tCK.AVG tJIT.PER tJIT(PER,LCK) tJIT.CC tJIT(CC,LCK) tERR.2PER tERR.3PER tERR.4PER tERR.5PER tERR(6-10PER) tERR(11-50PER) tCH.AVG tCL.AVG tJIT.DUTY
Average clock period nominal w/o jitter Clock-period jitter Clock-period jitter during DLL locking period Cycle-to-cycle clock-period jitter Cycle-to-cycle clock-period jitter during DLLlocking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles with n = 6 .. 10, inclusive
3000 -125 -100 -250 -200 -175 -225 -250 -250 -350
Cumulative error across n cycles with n = 11 .. -450 50, inclusive Average high-pulse width Average low-pulse width Duty-cycle jitter 0.48 0.48 -125
tCK.AVG tCK.AVG
ps
Rev. 1.3, 2007-05 07182006-DD60-22E6
52
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
7.4
ODT AC Electrical Characteristics
TABLE 53
ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400
This chapter describes the ODT AC electrical characteristics.
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
tCK
ns ns
2)
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
tCK tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
Rev. 1.3, 2007-05 07182006-DD60-22E6
53
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
TABLE 54
ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
nCK
ns ns
1) 1)2) 1) 1) 1)3) 1) 1) 1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
nCK
ns ns
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
nCK nCK
1) New units, "tCK.AVG" and "nCK", are introduced in DDR2-667 and DDR2-800. Unit "tCK.AVG" represents the actual tCK.AVG of the input clock under operation. Unit "nCK" represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, "tCK" is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
Rev. 1.3, 2007-05 07182006-DD60-22E6
54
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
8
Package Dimensions
FIGURE 8
Package Outline PG-TFBGA-84
This chapter describes the package dimensions.
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
Rev. 1.3, 2007-05 07182006-DD60-22E6
55
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
FIGURE 9
Package Outline PG-TFBGA-60
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
Rev. 1.3, 2007-05 07182006-DD60-22E6
56
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
9
Product Nomenclature
TABLE 55
Examples for Nomenclature Fields
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
Example for
Field Number 1 2 18 3 TC 4 256 5 16 6 7 0 8 A 9 C 10 -3.7 11
DDR2 DRAM
HYB
TABLE 56
DDR2 Memory Components
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology, consumer variant Component Density [Mbit] Values HYB 18 TC 256 512 1G 5+6 Number of I/Os 40 80 16 7 8 Product Variations Die Revision 0 .. 9 A B C 9 10 Package, Lead-Free Status Speed Grade C F -1.9 -2.5F -2.5 -3 -3S -3.7 -5 11 N/A for Components Coding Constant SSTL_18 DDR2 256 M 512 M 1 Gb 4 x8 x16 look up table First Second Third FBGA, lead-containing FBGA, lead-free DDR2-1066 DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
Rev. 1.3, 2007-05 07182006-DD60-22E6
57
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Chip Configuration for x8 components, PG-TFBGA-60 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ball Configuration for x16 components, PG-TFBGA-84 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Differential input waveform timing - tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Package Outline PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Package Outline PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Rev. 1.3, 2007-05 07182006-DD60-22E6
58
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Performance tables for -2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Performance table for -3(S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance table for -3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance table for -5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information for Lead-Free Products (RoHS Compliant). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDR2 Addressing for x8 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DDR2 Addressing for x16 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC & AC Logic Input Levels for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC & AC Logic Input Levels for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Input / Output Capacitance for DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input / Output Capacitance for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input / Output Capacitance for DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Input / Output Capacitance for DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 IDD Specification Parameters and Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IDDSpecification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Speed Grade Definition Speed Bins for DDR2-800E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Speed Grade Definition Speed Bins for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speed Grade Definition Speed Bins for DDR2-533C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speed Grade Definition Speed Bins for DDR2-400B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DRAM Component Timing Parameter by Speed Grade - DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DRAM Component Timing Parameter by Speed Grade - DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DRAM Component Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DRAM Component Timing Parameter by Speed Grade - DDR2-400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Rev. 1.3, 2007-05 07182006-DD60-22E6
59
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Average Clock and Jitter Symbols and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Jitter Value Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock-Jitter Specifications for -667 and -800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . ODT AC Characteristics and Operating Conditions for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 51 52 53 54 57 57
Rev. 1.3, 2007-05 07182006-DD60-22E6
60
Internet Data Sheet
HYB18TC256[80/16]0BF 256-Mbit Double-Data-Rate-Two SDRAM
Table of Contents
1 1.1 1.2 2 2.1 2.2 2.3 3 4 5 5.1 5.2 5.3 5.4 5.5 6 7 7.1 7.2 7.3 7.4 8 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Configuration for PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Configuration for PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 256-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Definition and Clock Jitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 25 27 29 34 34 37 50 53
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Rev. 1.3, 2007-05 07182006-DD60-22E6
61
Internet Data Sheet
Edition 2007-05 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

▲Up To Search▲

Price & Availability of HYB18TC256160BF-25

	To Download HYB18TC256160BF-25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .